1. Field
An embodiment of the present invention relates to integrated circuits, and more particularly, to a method and apparatus for reducing standby leakage current using a leakage control transistor that receives boosted gate drive during an active mode.
2. Discussion of Related Art
With the scaling of semiconductor process technologies, threshold voltages of semiconductor circuits are typically being reduced with reductions in supply voltages in order to maintain circuit performance. Lower transistor threshold voltages lead to significant increases in leakage current due to the exponential nature of sub-threshold conductance. Higher leakage currents lead to increased power dissipation which is undesirable for many semiconductor circuit applications. Higher leakage currents can be particularly problematic for mobile and handheld applications, for example.
One approach to addressing this issue has been to use multi-threshold voltage complementary metal oxide semiconductor (MTCMOS). An example of one MTCMOS scheme is shown in FIG. 1. In the MTCMOS approach of FIG. 1, low threshold voltage transistors are used for an internal circuit block 105 which is coupled to virtual power supply lines VVD and/or VGD. One or more higher threshold voltage transistors H1 and/or H2 are coupled in series between the internal circuit block 105 and the power supply lines VDD and/or GND, respectively. A standby signal STDBY and its complement STDBY#, which are used for active and standby mode control of the internal circuit block 240, are coupled to the gates of H1 and H2, respectively.
When STDBY is low, the internal circuit block 105 is in an active mode and H1 and H2 are turned on. VVD and VGD then function as the power supply lines for the internal circuit block 105. When STDBY is high, the internal circuit block 105 is in a standby mode and H1 and H2 are turned off. Leakage current of the internal circuit block 105 is suppressed due to the high threshold voltages of H1 and H2.
A disadvantage of this approach is that the higher threshold voltage devices H1 and H2 compromise the performance of the internal circuit block 105. Additionally, to maintain a low voltage drop between the power supply lines VDD and GND and the virtual power supply lines VVD and VGD, respectively, the linking devices H1 and H2 should be very large to reduce their resistance. Also, semiconductor processing of MTCMOS circuits is complicated by the need to provide transistors having multiple threshold voltage on the same integrated circuit die.
Another technique to reduce circuit leakage current uses substrate body bias to vary the threshold voltage of transistors in a circuit block for different modes. In this approach, during an active mode, a control circuit applies a voltage to the transistor bodies to zero- or reverse-bias the bodies with respect to the transistors. Upon entering a standby mode, the control circuit changes the substrate bias voltage to cause a reverse bias or deepen an existing reverse bias in the transistor bodies. In this manner, the threshold voltages of the transistors are increased during the standby mode to reduce or cut off leakage current.
A disadvantage of this approach is that a large change in body bias is required to change the transistor threshold voltages by even a small amount. Further, when changing from active mode to standby mode and vice versa, huge capacitances in transistor wells are switched from one voltage to another. Thus, significant power is dissipated during each mode transition.